1. Technical Field
The invention relates generally to gate leakage of MOS devices. More specifically, the invention relates to the reduction of gate leakage in MOS memory cells.
2. Discussion of the Prior Art
In the semiconductor manufacturing world the leading manufacturing processes are based on complementary metal-oxide semiconductor (CMOS) devices. The CMOS technology is in constant advancement, particularly by scaling down line widths, i.e., the minimal feature size for a given manufacturing technology, typically referred to as a process node. The decrease in feature size allows for improved performance of a CMOS device, evidenced by increased speed, reduced area, and increased functionality contained in a single chip. As line widths shrink it is generally observed that chip sizes are actually increasing. This happens because more functionality is packed onto these chips. Power dissipation is therefore one of the most pertinent problems of CMOS technology.
As the minimum feature size of a technology node is reduced so is the thickness of the gate oxide thickness as well as the power supply. The reduction of the power supply voltage is done to reduce the electrical field that develops across the oxide. For example, a typical 0.35 micron line width requires a power supply of 3.3V and gate oxide thickness of 70 Å; while in a 0.25 micron line width requires a 2.5V power supply and a 40 Å gate oxide thickness. Further reduction of the line width, for example to 90 nano-meters, requires the reduction of the power supply voltage to less than 1.0V and a further reduction of the gate oxide thickness. At these thicknesses of the gate oxide, significant tunneling current across the oxide is recorded. With the next generation of technology scaling to 65 nano-meters, a gate oxide thickness of less than 20 Å is used and the power supply voltage is further reduced to 0.7V. At this process node there is already recorded an extremely high level of gate current, causing concern that it has the potential of limiting the functionality of the CMOS technology.
It is known in the art that many solutions for reducing the gate current leakage are being sought, including the use of high dielectric constant insulators. However, no single solution has matured to provide production worthiness. A person skilled-in-the-art would further note that the problem caused by high leakage current through the gate oxide is found to be more severe in memory cells as compared to standard CMOS logic. In view of the limitations of the prior art, it would be advantageous to provide a solution to limit the gate current of CMOS transistors. It would be further advantageous if such a solution would be useful for the transistors used in memory cells, such as SRAM cells.